FPGA-based SHA-3 acceleration on a 32-bit processor via instruction set extension | NobleID

Main

Mint Work Search Explore Works Knowledge Graph Citation Graph Bibliometrics Receipts

v1

FPGA-based SHA-3 acceleration on a 32-bit processor via instruction set extension

Identifier:nobleid.org/w1/20260515/438861EB

Type:Journal Article

0 views

Support unavailableClaim Your Authorship

View Original Paper Source

Embeddable Badge

[![NobleID](https://www.nobleid.org/api/badge/438861EB.svg?ark=w1%2F20260515%2F438861EB)](https://nobleid.org/work/w1/20260515/438861EB)

ARK Inflections

Metadata Policy

Metadata Formats

Bibliometric Analysis

Impact metrics, research fronts, co-authorship networks →

Authors & Claims

Paper Authors

Claim authorship of this work

info@nobleid.org

About FAQ Terms Policy Persistence & Resolver Service Policy