v1
Joint sizing and adaptive independent gate control for FinFET circuits operating in multiple voltage regimes using the logical effort method
Identifier:nobleid.org/w1/20260515/FC0074F7
Type:Conference Paper
0 views
Embeddable Badge
[](https://nobleid.org/work/w1/20260515/FC0074F7)
Bibliometric Analysis
Impact metrics, research fronts, co-authorship networks →
Authors & Claims