Si/SnS2 Vertical Heterojunction Tunneling Transistor with Ionic-Liquid Gate for Ultra-Low Power Application

v1

Type:Conference Paper

0 views

[![NobleID](https://www.nobleid.org/api/badge/5ABC907D.svg?ark=w1%2F20260525%2F5ABC907D&value=id)](https://nobleid.org/work/w1/20260525/5ABC907D)

ARK Inflections

Bibliometric Analysis

Impact metrics, research fronts, co-authorship networks →

Authors & Claims

Paper Authors